Abstract
This tutorial paper presents a way to design a RISC simulator in software. Design concepts and sample 'C' implementation excerpts are shown to support the concepts. The tutorial does not assume prior
experience in programming a RISC processor. An understanding and appreciation of the RISC philosophy is desirable, yet, not mandatory.
This tutorial paper presents a way to design a RISC simulator in software. Design concepts and sample 'C' implementation excerpts are shown to support the concepts. The tutorial does not assume prior
experience in programming a RISC processor. An understanding and appreciation of the RISC philosophy is desirable, yet, not mandatory.
这篇论文介绍了如何用软件设计RISC模拟器。另外，没有RISC处理器编程经验的人也可以看看这篇论文。当然，有更好。
Keywords
RISC, CISC, pipeline, inter-locking,profiling
RISC, CISC, pipeline, inter-locking,profiling
Introduction
Before we plunge into designing a RISC processor simulator, let us spend a few moments in understanding the philosophical differences between the traditional RISC and CISC architectures. A quick look at the evolution of automated computing indicates a continuous improvement in the ease of programming vis-à-vis program complexity. This can primarily be attributed to the advent of 'high-level'programming languages, which liberated the computer programmer from writing code directly in machine or assembler languages.
我们先看看RISC和CISC两个架构之间的区别。
RISC vs CISC
CISC架构的设计目的是用最少的机器语言指令来完成所需的计算任务。这种架构会增加CPU结构的复杂性和对CPU工 艺的要求，但对于编译器的开发十分有利。今天只有Intel及其兼容CPU还在使用CISC 架构。相对于CISC架构，RISC架构把重点转移到软件上来了，它要求软件来指定各个操作 步骤。这种架构可以降低CPU的复杂性以及允许在同样的工艺水平下生产出功能更强大的CPU，但对于编译器的设计有更高的要求.
High-level programming languages are programmer-friendly but they introduce an unavoidable overhead of a multi-stage translation. A program in a typical high level programming language goes through a series of
complex transformations such as lexical analysis, parsing, code generation and optimisation before its equivalent machine code is produced.
高级程序语言对程序员是不错的，但是它也不可避免 的带来了多级翻译的问题(词法分析->解析->生成代码->优化 ->机器语言)。
Obviously, such a translation would be entirely unnecessary if the target processor directly interprets the constructs of the programming language. However, such an option is not scaleable as the programming
languages continue to grow in number as well as complexity. Imagine a system that needs an additional processor for every new programming language designed! It is precisely this problem the program translators address.
languages continue to grow in number as well as complexity. Imagine a system that needs an additional processor for every new programming language designed! It is precisely this problem the program translators address.
如果目标处理器能直接解 释程序语言的话，那么显然这种翻译是没必要的。但是随着程序语言的发展，它越来越复杂，这种选择是不能适应将来变化的 - 比如一个系统可能需要增加一个新的处理器来处理新的编程语言写的程序,而这正是程序翻译器干的事情。
The reign of CISC
Even as we rule out language specific processors as a solution, it seems desirable to have a good match between constructs of programming languages and instruction sets of generic processors. This makes
program translation easier as the code generator only needs to establish a mapping between the language constructs and the target processor's instruction set. This, in a nutshell, is
the CISC (Complex Instruction Set Computers) philosophy.
Even as we rule out language specific processors as a solution, it seems desirable to have a good match between constructs of programming languages and instruction sets of generic processors. This makes
program translation easier as the code generator only needs to establish a mapping between the language constructs and the target processor's instruction set. This, in a nutshell, is
the CISC (Complex Instruction Set Computers) philosophy.
我们排除了用针对特定语言的处理器作为解决方案的可能性，但是让编程语言和通用CPU指令集之间有一个很好的匹配还是很让人向往的。因为这让程序翻译更简单了 - 代码生成器只需要在语言和目标处理器指令集之间建立一个映射。这就是CISC的思想/思路。
The CISC philosophy reigned unchallenged for well over a decade in which it had as popular ambassadors, microprocessors from IBM, Digital, Motorola, Intel, Zilog and the like. These microprocessors supported a
large number of addressing modes, varied data processing instructions including complicated mathematical operations.
large number of addressing modes, varied data processing instructions including complicated mathematical operations.
CISC的思路曾经流行一 时，而且被很多流行的微处理器所采用，这些微处理器支持多种寻址模式，包括复杂数学操作的各种数据处理指令。
However, the CISC lunch did not come free. Complex micro-code (which consumed a significant portion of silicon on the real-estate starved chip), multi-cycle instructions (which blocked interrupts as long as they were executing!) and a performance that was slower as compared to memory offered by new technologies made CISC a good candidate for second choice. Only, the first choice was nonexistent.
但是CISC也不是完美无瑕 的。复杂的微码,多周期指令(它会阻塞中断直到它执行完毕).
The emergence of RISC
As the semiconductor industry strove hard to produce all-new and highly improved mousetraps, Ditzel, Hennessy and Patterson made a case for reinventing the whole wheel based on the principles of, what they termed, a "reduced instruction set computer" architecture. Some students at Berkeley took the RISC idea seriously and designed a simple processor by name " RISC I". This marked the beginning of the end of pure-CISC era.
几个人搞了一个"精简指令集计算机"架构,结束了CISC独霸的局面.
The RISC architecture was based on a simple observation that most programs spent most of their time (over 70%) in moving data between the processor and memory, and in making program control decisions
based on that data. RISC designers devoted most of their attention towards making processors that run faster for these frequently used instructions. These processors had their functional units (ALU, register
files, decode logic, control signal logic etc.) organised so as to be operated in parallel. This allowed for splitting the lifecycle of each instruction into multiple phases, with one functional unit per phase. This approach, known as 'pipelining' closely resembles the assembly line in a manufacturing industry. Fig.1 is a snapshot of on such three-stage instruction pipeline. The lightly shaded portion shows the
stages that would be executed in the future while the darkly shaded portion shows those that are completed.
based on that data. RISC designers devoted most of their attention towards making processors that run faster for these frequently used instructions. These processors had their functional units (ALU, register
files, decode logic, control signal logic etc.) organised so as to be operated in parallel. This allowed for splitting the lifecycle of each instruction into multiple phases, with one functional unit per phase. This approach, known as 'pipelining' closely resembles the assembly line in a manufacturing industry. Fig.1 is a snapshot of on such three-stage instruction pipeline. The lightly shaded portion shows the
stages that would be executed in the future while the darkly shaded portion shows those that are completed.
RISC 架构基于一个简单的事实 - 许多程序把70%的时间花费在处理器和内存之间移动数据,而这些数据影响着程序结果. RISC的设计者把注意力集中在如何让那些被频繁使用的指令执行的更快.这些处理器把它们的功能单元(ALU,寄存器文件,译码逻辑,控制逻辑等)组织起 来并行的运行.这使得每一条指令的生命周期被划分成多个阶段 - 一个功能单元一个阶段. 这就是pipelining(流水线操作/流水线作业).
Each instruction enters the pipeline from the memory retires after completing execution. Of the five instructions shown in the figure, only three are in the pipeline, in various stages of execution. The first
instruction has completed its three stages and has retired. The fifth instruction is in the memory and is yet to enter the pipeline. In the current clock cycle (shown as 'Clk' in the figure), the processor
parallely executes the E-stage of instruction-2, D-stage of 3 and F of 4. This is made possible by a design, which ensures that no two active stages require the same processor functional unit simultaneously (i.e., in the same clock cycle).
instruction has completed its three stages and has retired. The fifth instruction is in the memory and is yet to enter the pipeline. In the current clock cycle (shown as 'Clk' in the figure), the processor
parallely executes the E-stage of instruction-2, D-stage of 3 and F of 4. This is made possible by a design, which ensures that no two active stages require the same processor functional unit simultaneously (i.e., in the same clock cycle).
每条指令从内存进入流水线,执行完然后退出. 图中的5条指令只有3条在流水线里面. 第一条指令已经完成它的3个阶段/流水线站并退出.第5个指令在内存中还没有进入流水线.在当前的时钟周期(图 中'Clk'那列),处理器并行执行第2,3,4条指令的W,D,F阶段. 这就保证了没有两个指令的阶段会同时请求同一个处理器功能单元 - 比如,在一个时钟周期内,没有两个指令会同时要求处理器处理它的E/D/F阶段.
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